While there are various modifications in the art of dual damascene process, FIGS. 11A-11F show a typical conventional method of forming a multilayer interconnection structure that uses a dual damascene process.
Referring to FIG. 11A, a Si substrate 10 is covered by an interlayer insulation film 11 of a CVD-SiO2 film, and the like, and an interconnection pattern 12A is formed on the interlayer insulation film 11. The Si substrate 10 carries thereon various semiconductor device elements such as MOS transistors not illustrated.
The interconnection pattern 12A is embedded in a next interlayer insulation film 12B formed on the interlayer insulation film 11 to form an interconnection layer 12, wherein the interconnection layer 12 is covered by an etching stopper film 13 such as an SiN film. The etching stopper film 13 is further covered by a next interlayer insulation film 14.
In the step of FIG. 11A, a resist pattern 18 is formed on the interlayer insulation film 14 by a photolithographic process such that the resist pattern 18 has an opening 18A corresponding to a contact hole to be formed, and the interlayer insulation film 14 is removed by a dry etching process while using the resist pattern 18 as a mask. As a result of the dry etching process, there is formed an opening 14A in the interlayer insulation film 14 in correspondence to the contact hole to be formed.
Next, in the step of FIG. 11B, the resist pattern 18 is removed and a resist film 19 is formed on the structure of FIG. 11B in the step of FIG. 11C so as to fill the contact hole 14A. By patterning the resist film 19 thus formed by a lithographic process, a resist opening 19A is formed in the resist film 19 in correspondence to the interconnection pattern to be formed.
Next, in the step of FIG. 11D, the exposed part of the interlayer insulation film 14 exposed at the resist opening 19A is patterned by a dry etching process while using the resist film 19 as a mask. Thereafter, the resist film 19 is removed. As a result of such a patterning process, an opening 14B is formed in the interlayer insulation film 14 in correspondence to the desired interconnection groove in addition to the contact hole 14A.
Next, in the step of FIG. 11E, the etching stopper film 13 is removed by a dry etching process that uses an RIE process, and the interconnection pattern 12A is exposed.
Next, in the step of FIG. 11F, the interconnection groove 14B and the opening 14A are filled by a conductive film of Al or Cu. By applying a chemical mechanical polishing (CMP) process to the structure thus obtained, an interconnection pattern 20 is obtained in electric connection with the interconnection pattern 12A by the contact hole 14A.
By repeating the foregoing process steps, it is possible to form third and forth interconnection patterns.
In such multilayer interconnection structure for use in a semiconductor device, it is important to use a low-dielectric insulation film for the interlayer insulation films 12 and 14 so as to reduce the stray capacitance of the multilayer interconnection structure. By reducing the stray capacitance, the operational speed of the semiconductor device is improved. Thus, various attempts have been made to use a low-dielectric material for the interlayer insulation film 12 or 14, such as F-doped SiO2 film (SiOF film), organic Si insulation film (SiOCH film), and the like. By using an organic Si insulation film, in particular, it is possible to realize a specific dielectric constant of 3.0 or less.
In such a process of forming a multilayer interconnection structure by a dual damascene process, the role of the etching stopper film 13 is important as noted previously. Conventionally, a SiN film, which shows a large etching selectivity with regard to the interlayer insulation film 14, is used extensively for this purpose. In the art of dual damascene process, the etching stopper film 13 is not only required to have a large etching selectivity but also to act as an effective barrier against diffusion of metals such as Cu that constitute the interconnection pattern. Further, the etching stopper film is required to have excellent adhesion with regard to the interconnection pattern and further to the interlayer insulation film. In addition, the etching stopper film is required to have excellent resistance against plasma ashing process or wet etching process. It is known that an SiN film functions as an efficient diffusion barrier.
Conventionally, an SiN film has been formed easily by a plasma CVD process. On the other hand, an SiN film thus formed has a large dielectric constant of 7-8. Thus, the effect the stray capacitance reduction achieved in the multilayer interconnection structure by the use of low-dielectric insulation film for the interlayer insulation films 12 and 14 is substantially cancelled out by the use of the SiN etching stopper film 13.